Prof. Y. V. Joshi completed Bachelor of Electronics Engineering in 1986, Masters of Electronics Engineering in 1991 (both from SGGS Institute of Engineering and Technology, Vishnupuri, Nanded) and a Ph.D. in 1998 (from IIT, Delhi).  He is member of IEEE, Fellow of Institution of Engineers (India), Fellow of IETE (India) and a life member of ISTE.
Before joining as Director on 23-Apr-2018, he was working as Professor of Electronics and Telecommunication Engineering at SGGS Institute of Engineering from July 2001. Prior to this he was Assistant Professor (1993 to 2001) and Lecturer (1986 to 1993) at the same department.
He worked as Director, Walchand College of Engineering, Sangli (2009 to 2013). He also worked in various capacities such as Head of Department (2002-2004), Dean(Academics) (2004-2006), Dean (Resource Mobilisation)(2007-2008), Registrar (2014-2016) at SGGS IE&T, Nanded.
His subjects of interest include Signals and systems, Digital Signal Processing, Adaptive Signal Processing, Modern Digital Design using Verilog, VLSI Design, etc.  Nine students have completed Ph.D. under his guidance and research work of eight Ph.D. research scholars is in progress. He also supervises students for M.Tech. and Ph.D. in signal processing and allied areas. He has also conducted several short duration Faculty development programs at SGGSIE&T, Nanded. He has to his credit more than 30 International Journal Papers and more than 60 National and International Conference publications.
He visited USA (2016), Dubai (2015), Malaysia and Singapore (2013) and China and Hongkong (2016) for presenting papers and discussions with academia. He chaired two sessions as Session Chair in International Conference IEEE/MTS Oceans during 19th to 23rd Sept 2016, in the USA. Three alumni meets of SGGS Engineers’ Alumni Association (North America Chapter) were organised and conducted on 17th Sept at New Jersey, 24th Sept at San Jose and 1st Oct at Atlanta, in the USA. He also visited 8 Universities related to infrastructure, Incubation Center, laboratories, projects and met a few Faculty and studied the possibility of collaboration with reference to credit transfer, student and faculty exchange and research collaborations with City University New York, San Jose state University, University of California, San Diego, Oakland University, Detroit, Buffalo University, Indiana University Purdue University, Indiana, Purdue University and Georgia Tech University. He has also successfully completed the research project sponsored by All India Council for Technical Education (AICTE), New Delhi. He worked as resource person for many CEPs, attended many short term courses and participated in workshop/conferences organized by different national/international agencies.
He was instrumental in starting a new PG programme M.Tech. (Embedded Systems and VLSI Design) from AY 2015-16 with an intake of 18, with major focus on Industrial participation in teaching and learning process and established Industry sponsored Laboratory (“Center for VLSI Design and Verification”) from Mentor Graphics with software support worth Millions of US Dollars. He also is credited to bring DST-FIST funds for of strengthening PG laboratory in VLSI for Rs. 47.50 Lakhs.
He worked on various committees formed by NBA/AICTE/DTE/UGC/Universities. He was nominated as a TEQIP II mentor for Government college of engineering, Jagdalpur, Chandigarh, and performance auditor for institutes in Gujrat (2) and Punjab (2).  He was also nominated as NEQIP performance cum financial auditor in North Eastern State Manipur. He is member of Academic Council, Swami Ramanand Teerth Marathwada University, Nanded and Dr. Babasaheb Ambedkar Technological University, Lonere.